As a Sr. FPGA Design Verification Engineer, supporting the Roche DNA Sequencing unit, you will be responsible for all aspects of the verification of Genia’s FPGA designs and will contribute to the verification of ASIC designs, including block-level and chip-level functional test plan development, test bench and model’s creation, detailed verification of every aspect of the chip functionality. In addition, you will engage in other aspects of design verification, including front-end architecture planning, system modeling, external IP integration verification, flow development, and EDA tool evaluation and selection.
- Ownership of all aspects of the design verification of the FPGA chips and/or its functional blocks
- Test Plan ownership, and coordination with Architecture, Design, DFT, and other teams to deliver a complete, comprehensive verification plan
- Ownership of system, chip, and IP models for verification
- Evaluation and selection of flows and EDA tools
- Development and deployment of processes and flows for Design Verification